Amazing, from 2″ to 17″ wafer sizes in 35 years!

In January my son, Steve, popped into the Intel museum in Santa Clara, California to look at the 4004 display mentioned in a previous post.

He came back with various photos some of which showed how semiconductor wafer sizes have increased over the last 30 years. This is the most interesting one.

1969 2-inch wafer containing the 1101 static random access memory (SRAM) which stored 256 bits of data.

1972 3-inch wafer containing 2102 SRAMswhich stored 1024 bits of data.

1976 4-inch wafer containing 82586 LAN co-processors.

1983 6-inch wafer containing 1.2 million transistor 486 microprocessors

1993 8-inch wafer containing 32Mbit flash memory.

2001 12-inch wafer containing Pentium 4 microprocessors moving to 90 nanometer line widths.

Bringing the subject of wafer sizes up to date, here is a photo of an Intel engineer holding a recent 18-inch (450mm) wafer! The photo was taken by a colleague of mine at the Materials Integrity Management Symposium – sponsored by Entegris, Stanford CA June 2006.

The wafer photo on the left is a 5″ wafer from a company that I worked for in the 1980s called European Silicon Structures (ES2). They offered low-cost ASIC (Application Specific Integrated Circuit) prototypes using electron beam beam lithography rather than the more ubiquitous optical lithography of the time. The technique never really caught on as it was uneconomic, however I did come across the current use of such machines in a Chalmers University of Technology in Göteborg, Sweden if I remember rightly.

If you want to catch up with all the machinations in the semiconductor world take a look at ChipGeek.

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